Microelectronic circuitry uses isolation trenches filled with electrically isolating materials to electrically isolate the individual devices comprising integrated circuits from one another. Abrupt transitions between active and isolation regions are necessary to maximize circuit density. Shallow trench isolation is one means for achieving the necessary abrupt transition. Typical trench fabrication methods feature the etching of vertical walled trenches between active circuit areas, then filling the trenches with electrically isolating material (typically silicon dioxide), thereby electrically isolating independent circuit portions. Existing trench fabrication technologies stress the need for creating trenches with nearly vertical trench walls in order to achieve the requisite abrupt transition between active and isolation regions. In doped wafers, the walls and floors of these isolation trenches are heavily doped increasing their isolating effect and improving the reliability of circuit interconnections. Standard vertical wall trenches present numerous difficulties to the doping process. In order to dope the vertical trench walls the entire surface is angled allowing implantation of the trench walls. Unfortunately, this process does not create a uniformly doped trench with any useful degree of reliability. Moreover, in deep narrow trenches it becomes very difficult to dope the bottom segments of trench walls. Thus, the need to facilitate doping and the need for deep narrow trenches are at cross purposes. Additionally, the nearly vertical walls create sharp angles (nearly 90.degree.) at the trench corners (e.g. angle .theta. of FIG. 15) which lead to enhanced edge conduction. The sharp edges also cause difficulties in controlling, for example, gate oxide uniformity at the corners. These sharp angles are known to cause electrical failures in integrated circuits and are a serious cause of circuit unreliability. These problems are known as edge effects. Additional problems arise when trenches are doped and used as current paths. For example, in addition to edge effects, vertical walled trenches are prone to contact misalignment which leads to contacts shorting against the substrate and self-aligned gate shorting. This leads to catastrophic circuit failure.
Other existing isolation processes exhibit similar problems, as well as unique problems of their own. For example, the so-called LOCOS method, which selectively oxidizes patterns on a silicon substrate to create isolation regions, suffers from oxide encroachment of silicon dioxide under the silicon nitride layer. This oxide encroachment is known in the industry as a bird's beak. This bird's beak problem reduces the active circuit area between the isolation regions by encroaching into the active regions. As feature size decreases this becomes a more significant problem. Other known processes include a variation of the LOCOS process which is known in the industry as SWAMI, as developed by Hewlett-Packard. The SWAMI process includes outwardly etching the silicon nitride and the pad oxides at 60 degrees such that the subsequent oxidation and beak formation length is limited. Still other methods include using high-pressure oxidation techniques where the oxide is grown faster and at a lower temperature. This results in minimizing the growth of the bird's beak. But, in the end, all of these methods suffer from the bird's beak problem which reduces the active surface area, thereby limiting circuit density.
The primary object of the present invention is to reliably fabricate sloped wall isolation trenches which avoid self-aligned source shorting and contact misalignment shorting. Another object is to provide isolation trench profiles which are more easily doped, thereby creating a more reliable isolation trenches. Another important object is the fabrication of sloped wall isolation trenches which reduce edge effects and thereby increase circuit reliability. A related object of the present invention is to provide an isolation trench which does not suffer from the bird's beak problem and thereby conserves the maximum amount of microchip surface area.
Finally, the present invention provides fabrication processes for manufacturing microelectronic integrated circuit structures featuring isolation trenches with reliably sloped walls in accordance with the foregoing objects. The key objective of the invention is to overcome the difficulties presented in reliably producing trenches with controlled slope walls.